DDR vs. SDR RAM...

Hi Clancy,

So is the controller pipelined then? Is that the reason Altera can claim one cycle access? Does it pump out successive words every clock after the 7?

Have you learned enough to account for all 12 cycles on the back to back reads from the same row?

Do you think its inevitable or can something be done?

I need fast 15bit table lookups so what I did was respin my Cyclone/SDRAM board with Stratix and SRAM. I should have protos next week. I would like to be able to go back to Cyclone/SDRAM if the core+controller can be made workable.

Thanks,

Ken