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Altera_Forum
Honored Contributor
Honored ContributorDDR vs. SDR RAM...
Anyone know if DDR Ram will fare better with the NiosII data master than SDRAM? After Dirk figured out it takes a whopping 12 clocks @50MHz (~240ns) per SDRAM read when not using the dma, we re...
Altera_ForumHonored Contributor
Honored ContributorHi Ken,
I don't know if you read my previous posts, or they were a bit confusing, but looking at the HDL code generated by SOPC Builder for the Avalon SDRAM controller and at the SDRAM datasheet I see that it takes 7 clocks from the moment the controller gets the read request until it puts the readdata back onto the bus (for CAS latency = 2), assuming that the row is already active and we don't need the RAS phase.
