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Altera_Forum
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21 years ago

DDR vs. SDR RAM...

Anyone know if DDR Ram will fare better with the NiosII data master than SDRAM? After Dirk figured out it takes a whopping 12 clocks @50MHz (~240ns) per SDRAM read when not using the dma, we re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi James,

Can you elaborate on NiosII/f SDRAM access? Jesse indicated the largest part of the problem was that the NiosII/f data master was not "Latency Aware".

So anything not dma'd or read out of the cache incurs a large timing hit as demonstrated in the other thread on this topic -even if the reads are back to back in the same bank.

A work around or a glimpse of the roadmap would sure be welcome.

Thanks,

Ken