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Altera_Forum's avatar
Altera_Forum
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21 years ago

DDR vs. SDR RAM...

Anyone know if DDR Ram will fare better with the NiosII data master than SDRAM? After Dirk figured out it takes a whopping 12 clocks @50MHz (~240ns) per SDRAM read when not using the dma, we re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi,

Is it a solution to use another type of SDRAM controller that runs on a higher clock speed than the Nios. I think SDRAM can handle more than 100Mc as input clock.

Then probably you can reduce 12 clocks on 50 Mc to 12 clocks on 100Mc.

Can you try to run your Nios on a higher clock frequency? Eventually using another speed grade for the FPGA? I think 80 to 100Mc must be possible, depending on the number of peripherals you connect to the avalon bus.

Stefaan