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Altera_Forum
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13 years ago

DDR SDRAM won't fit!

Hi All, I am using a cyclone III starter kit, which has the EP3C25F324C6 FPGA on and the zentel A3S56D40ETP-G5 SD-RAM. I have (i think) added the DDR ram controller in QSYS correctly (I used ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I was able to fix this issue by modifying the pin assignments. (ex: mem_dqs_to_and_from_the_ddr2_bot[0] set to SSTL-18 class I (as suggested in the flow messages )) and by back annotating the pin assignments made during the compilation phase.