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Altera_Forum's avatar
Altera_Forum
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14 years ago

DDR and DDR2 as a main memory

Hi folks.

I am in troubles now. In my system i have two(2) boards. First(with Cyclone III) has a DDR memory and i need it to use as a main memory for NIOS core. The second

one(with Aria GX II) has DDR2 memory and i need it to use as a main memory for NIOS core.

Briefly, it does not work.We tried everything. In HW design (in Quartus) we tried to connect DDR directly to CPU(NIOS),tried to connect it via the bridge exactly according the design,which has been found

on:http://www.altera.com/support/examples/nios2/exm-multi-nios2-hardware.html

Nothing.I tried to DEBUG(not to program flash) via USB-Blaster and I even cannot start debuging.

Maybe i must in this case, to program flash? Maybe in this case it is not possible to debug(i do not believe) application for NIOS?

Help me guys, it is very urgent.

Thank you all,Slava.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You are going to have to be a little more descriptive of "it doesn't work". What error messages are you getting, what are you trying exactly, does something hang or error out or get a warning? Where are your reset and exception vectors pointed to? Are you using the bottom few address spaces in the ddr? I have a faint memory that you are not suppose to use them as they get changed with calibration or something, but can't think of where i remember that from. Does you system come out of reset? Do you have valid clocks everywhere they are used? Does the DDR pass calibration? Have these boards been tested or worked with other designs, just not with your current design? Have you tried to run a simple hello world program running from ddr? Have you tried to run a simple hello world program with a nios system not connected to ddr just to verify you have working knowlege of the nios ide and that your board generally works?

    Just a few thoughts that will help figure out what the problem is.

    Kevin
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    What error messages are you getting, what are you trying exactly, does something hang or error out or get a warning?

    --- Quote End ---

    On both of boards i do not get any message.I mean i can not start debug.

    Message, i get when i am trying to start is:

    using cable "usb-blaster [usb-0]", device 1, instance 0x00

    pausing target processor: not responding.

    resetting and trying again: failed

    leaving target processor paused

    --- Quote Start ---

    Where are your reset and exception vectors pointed to?

    --- Quote End ---

    Now Reset vector and exception vector are pointing to DDR memory. Now i do not have in my design(temporary) EPCS memory.

    --- Quote Start ---

    Does you system come out of reset?

    --- Quote End ---

    Yes

    --- Quote Start ---

    Do you have valid clocks everywhere they are used?

    --- Quote End ---

    I am pretty sure, that YES.

    --- Quote Start ---

    Does the DDR pass calibration?

    --- Quote End ---

    I do not know. What is this DDR calibration and how to perform it, if i need/must?

    --- Quote Start ---

    Have these boards been tested or worked with other designs, just not with your

    current design?

    --- Quote End ---

    One of the boards(the board whit DDR and not with DDR2) is working with other design, and the second one - i didn't see him working.

    --- Quote Start ---

    Have you tried to run a simple hello world program running from ddr?

    --- Quote End ---

    For design with DDR I am trying simple "Hello word" application ONLY and it does not work.

    --- Quote Start ---

    Have you tried to run a simple hello world program with a nios system not connected to ddr just to verify you have working knowlege of the nios ide and that your board generally works?

    --- Quote End ---

    One of the boards(the board whit DDR and not with DDR2) it is working great, but for second one ,as i said before - i didn't see him working.

    Thank you,Kevin.

    Slava.
  • Altera_Forum's avatar
    Altera_Forum
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    I recommend starting small and working your way up. Build a simple design with Nios II, JTAG UART, on-chip memory, SDRAM. Either write your own memory test software or try "memtest" or the smaller version of it that is available in eclipse. Once you validate your memory then you work your way up to doing something more sophisticated like multi-core design.

    Also with the DDR2 SDRAM based design did you remember to handle the OCT interface? There should be signals named "rup" and "rdn" that require connectivity as well. These signals were not present for your DDR (one) controller since they are only part of the JEDEC DDR2 and DDR3 specs.
  • Altera_Forum's avatar
    Altera_Forum
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    Sorry for the delayed response, been busy.

    From my experience, when it fails to pause the processor, I either have a reset incorrect or a clock that is not running, thus it never comes out of reset.

    I agree with BadOmen, start small and work your way up. Not just with the IDE and procramm running, but the whole SOPC project. You said on the DDR board you have an example design working, start from that and add DDR but still run the program out of internal mem, then try and run it from DDR, and see if you can make that process work. For the DDR2 board, if you found your error with the DDR board then work from that, else start the same basic process over.

    Make use of signaltap need be. You can route all of your clocks and resets to it, then you will know if everything is up and running or not.

    @BadOmen, the rup and rdn do not require connectivity to use OCT i don't believe, only if you want to use calibrated OCT. You can use uncalibrated OCT without those connections, although it is less desirable. Correct me if I am wrong though.