DDR and DDR2 as a main memory

I recommend starting small and working your way up. Build a simple design with Nios II, JTAG UART, on-chip memory, SDRAM. Either write your own memory test software or try "memtest" or the smaller version of it that is available in eclipse. Once you validate your memory then you work your way up to doing something more sophisticated like multi-core design.

Also with the DDR2 SDRAM based design did you remember to handle the OCT interface? There should be signals named "rup" and "rdn" that require connectivity as well. These signals were not present for your DDR (one) controller since they are only part of the JEDEC DDR2 and DDR3 specs.