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Altera_Forum's avatar
Altera_Forum
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15 years ago

dataavailable signal on Avalon MM

I have a MM slave that has to read an external device, and due to the latency in the read process to this device, I would like to have my Nios initiate the process by a write to a register and then r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Remember that the Avalon bus is 'slave arbitrated'.

So that during the long cycle only the master (nios) and other accesses to the same slave are stalled.