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Altera_Forum
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11 years ago

Data transfer between fpga (14 bits) vhdl block to NIos II system (16 bits)

Hi, I am writing C code to program Altera Nios II system in Cyclone IV E. The Nios II system is used to control some custom FPGA blocks written in VHDL in Quartus II. In the vhdl block ...
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Altera_Forum
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11 years ago

Why can't you adjust your VHDL code to output and accept 16 bit data. That seems like the simplest approach. Also, since all you are doing is scaling, why wouldn't you do this operation also in VHDL. You are creating a huge bottleneck in your data flow by using the NIOS to scale your data. Floating point operation in software are incredibly slow... Ideally, the NIOS should not be doing data processing, it should just be doing management.