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Altera_Forum's avatar
Altera_Forum
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19 years ago

data loopback problem

I have a custom Cyclone board with a USB interface chip (Cypress). All software i/o operations are via IORD and IOWR macros. I am using the small non-cached niosII processor. I have written ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

How are you determining that you have data available (polling or interrupt-driven)?

Have you considered using a DMA to process this? It seems like it would make sense to do so..... or design the DMA/streaming capability into your USB peripheral(s) itself. In this way, you'd just use the processor to configure your endpoints and then wait for interrupts from them (or your DMA).

Cheers,

- slacker