update:
I have had little luck on this front. I have now tried all three Nios core options, i.e., non-cached, instruction-cached, and data&instruction-cached. I was not able to find any combination of C-code which would successfully run with either of the cached processors. I used various types of declarations, "volatile"s, and looping structures. It is curious that semi-working code (using previously mentioned "magic" printf) would become completely inoperable code by switching cores and yes, I rebuilt the project (the code and associated libraries). Notably, the cached cores seemed to fail while talking to the USB chip by ignoring the BUSY line. Simple while loops were in place to monitor the busy flag and write only when the chip was not busy. See code below:
while ((IORD_ALTERA_AVALON_PIO_DATA(USB_STATUS_PIO_BASE)&0x01) != 0x01); //wait until not busy
IOWR(USB_SX2_BASE, 0x04, (0x0030 | 0x0080)); //Write request, bit7 = 1, bit6 = 0
This worked in the non-cached but not either of the cached versions. hmmmm.
end run: I decided to try the DMA approach. I added a DMA controller to the Nios processor connecting the DMA ports to the peripheral and the on-chip data memory. While the resulting compilation ended up with additional timing errors, none of the timing violations were associated with logic used for the USB interface. I used C-code which was working immediately prior to adding the DMA controller and no longer ran. I changed the DMA port connections to Nios components not associated with the USB peripheral and regenerated/compiled. The program executed without problems. It seems that the DMA controller is affecting timing of the internal busses.
punt At this point I need to stop my development on USB and focus on other functions of the board. This USB portion has consumed too much of my developing time budget and must move forward on other avenues. I will hopefully return to this problem within a couple months but frankly, I'm not sure where to go with it. Perhaps this break will allow me to think of new approaches to the problem.
My suspicions are timing issues. I just haven't found what needs to be tighter constrained. I have had previous erratic behavior on this board while developing code for another off-chip peripheral and "solved" the problem by changing timing constraints. Another alternative which is not very pleasant to think about, is a possible layout issue. This board is a six layer board: L1 - GND plane with some escape routing, L2 - signal w/ GND fill, L3 - split plane for core power, PLL power, L4 - +3.3V plane, L5 - signal w/ GND fill, L6 - GND plane. There are multiple 0.01/0.001uf SMD caps located at each corner of the 400-pin BGA. I don't see where I missed something but ???
Here's some of the working code, as promised. Below the first excerpt is a different looping structure which was less succesful although it was possible to eventually get it to work. Curiously, on the second version, removal of the "j=0" line would keep the code from executing properly although the variable J has absolutely nothing to do with the loop.
Not sure where to go from here. Thanks for your input.
steve
Working code:
void USB_data_loopback(void)
{
volatile alt_u8 i,j,flag_statusOUT,flag_statusIN;
alt_u16 data[128];
no_activity = 1;// clear flag
if (got_out_data) //The FLAGS int tells us we have out data
{
got_out_data = 0;
if (IORD_ALTERA_AVALON_PIO_DATA(USB_STATUS_PIO_BASE)&0x02)
{
j = 0;
while(IORD_ALTERA_AVALON_PIO_DATA(USB_STATUS_PIO_BASE)&0x02)
{
data[j] = IORD(USB_SX2_BASE, 0x00);
j++;
}
printf ("0/2 %x \n",j); //magic printf
for (i = 0; i < j; i++)
{
IOWR(USB_SX2_BASE, 0x02,data[i]);
}
}
..
..
..
..
Other structure:
void USB_data_loopback(void)
{
volatile alt_u8 i,j,flag_statusOUT,flag_statusIN;
alt_u16 data;
no_activity = 1;// clear flag
if (got_out_data) //The FLAGS int tells us we have out data
{
got_out_data = 0;
if (IORD_ALTERA_AVALON_PIO_DATA(USB_STATUS_PIO_BASE)&0x02)
j = 0;
while(IORD_ALTERA_AVALON_PIO_DATA(USB_STATUS_PIO_BASE)&0x02)
{
data = IORD(USB_SX2_BASE, 0x00);
IOWR(USB_SX2_BASE, 0x02,data);
}
..
..
..
..
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