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Altera_Forum's avatar
Altera_Forum
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21 years ago

Data bus sharing and user component with HDL files

Hi all, When I create a new tristate slave component for the NIOS/SOPC builder and the component is implemented using some custom logic in VHDL code, the SOPC builder adds a new data bus for th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

1. tristate-Data_bus and address_bus should be directly ported out to external device

2. the signals of above components could be added LOGIC in FPGA before being ported out ot external device