Data bus sharing and user component with HDL files

Hi,

In the case of a tristate bus, you have both options: simply mapping the avalon signals to ports for being connected to the external fpga chip, or including an HDL file (or files) for including hardware into the system.

Some chips have a very simple interface and need nothing else but simple connections to the corresponding avalon bus signals, but some others have a rather than simple interface and require special timing and signals which are not a simple combinational logic from the avalon bus signals, which is our case.