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Altera_Forum
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11 years ago

Data acquisition at both edge of the clock: Signal Tap logic II analyzer

Hi, can Signal Tap II logic Analyzer be used for data acquisition at both rising and falling edge of the clock? I need it for test purpose. I am using TSE MAC in RGMII mode. When I put Signal...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

I think by doubling frequency of sample clock being used in Signal Tap analyzer you can achieve your goal. I mean using PLL, generate one clock having frequency double than what you are using currently and use that PLL output as sampling clock in signal tap.

Cheers,

Bhaumik