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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone IV EPCS controller read info. failed

The thing i want to do is implementing a remote update system 'factory' image that could boot from EPCS64 and give user a selection to choose reconfiguring FPGA and booting from another image.

The hardware SOPC system i constructed contains one EPCS controller, one c iii remote update core and sdram etc. Then i write some code to write the application hardware image into the latter space of EPCS device, and it works well. But after one recompile of my sopc system and quartus ii project. The software starts to behave badly. The phenomenon is i need to run the software twice until i could get the right info. from epcs device (the first time it returns false info.). Finally, the software completely don't work.

The only difference is at first, SOPC builder don't expose the dedicated EPCS pins to the top level design. But after the recompile action, it expose the four pins to the top level but i don't know how to put pin assignments for them.

I'm using the quartus 10.0 and nioseds 10.0.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    When i revert back to 8.0, and using c iii, the sopc builder correctly generates the expected four epcs pins. After set them on 'dual purpose pins' tab as 'using as regular I/O', i could assign them pin locations and successfully use software access it.

    When using 9.1 sp2, the sopc builder does not expose the four epcs pins on the top instance. But leave the 'Dual purpose pins' tab with default value, i could also access the epcs device despite during compilation there is warnning info. indicates that ignored pin assignment to DCLK...etc.

    Unfortunately, 10.0 do expose these four pins to the top level but do not let users set three of the four pins as 'regular I/O'. so .........
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Unfortunately, 10.0 do expose these four pins to the top level but do not let users set three of the four pins as 'regular I/O'. so .........

    --- Quote End ---

    This is a new bug in the Quartus II 10.0 GUI. You can get around it by editing your settings file directly. See this related thread (http://www.alteraforum.com/forum/showthread.php?p=95053#post95053) for details.