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praveenkumar's avatar
praveenkumar
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone III - Nios II - Starter board

On programming through jtag (usb blaster)

verify failed between onchip memory locations some xxxxx and xxxx.

likethat it showing an error anyone help me about this

2 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Can you show me the exact error message that you got?


    Also, how do you do programming? Are you programming the FPGA using Quartus Programmer or via NIOS II?


    Regards,

    Bruce


    • praveenkumar's avatar
      praveenkumar
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      i am programming with both .sof file from quartus programmer and .elf file from nios ii.

      while programming from quartus programmer its working fine .but on loading with nios ii .its comming error verify failed betweeen memory locations 0x40000and 0x43270 like that i dont understand the cause of this error.

      jtag is detecting .

      and also i have another doubt .

      while assigning the pin assignments in cyclone iii

      part number EP3c80ufbga484i7

      error shows while compiling like can't fit the design in fitter and placing.

      can't place multiple pins assigned to pin location D1,k1,e2.

      i checked all the other pins i didnt place these any where in pin planner .

      its showing pin d1 assigned to ALTERA_ASDO_DATA

      pin e2 to ALTERA_FLASH_nCE_nCSO.

      like that.

      but we didnt route these pins to those assigned pins.

      i want to know if these pins are reserved or something else

      please find a solution for this also