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Honored Contributor
Honored ContributorCyclone Ii To Adc Interface Problems
ADC Interface Problems ======================= I am using a Cyclone II Fpga. I am trying to interface between a Nios Processor and a two serial output Linear ADCs LTC 1867(16 bit) for data acq and...
Altera_ForumHonored Contributor
Honored ContributorYou didn't tell a word about intended ADC throughput. Generally I would prefer a generic HDL (Verilog or VHDL) design for the data acquisition and preprocessing task, at least for medium or higher speed. It can deliver the data to the SOPC design part, e.g. through a FIFO or a dual port memory.
