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Altera_Forum
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21 years ago

cyclone 1c20f400c7

Hi, I am new to altera FPGA and its NiosII. I got below problems need your great help: 1, I add some pio, uart and spi port in Full_featured example then built it without any errors. 2, In IDE, ...
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Altera_Forum
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21 years ago

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originally posted by james@Jul 18 2005, 04:45 PM

does your reset address points to volatile memory such as dram?

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Hi ,James,but what might be the pending result if I make reset address to a volatile memory?