Forum Discussion
Altera_Forum
Honored Contributor
20 years agoLittle more info...
I set the .dat file to initialize the flash device upon simulation start. So, now I can see what's going on with real data. It appears that my thinking on how the data bus is filled was correct, but there are some weird things with 'waitrequest'. It seems that 'waitrequest' in the sim drops low for a <1ns period of time somewhere around 2/3 of the way through the read cycle (according to the sim)... Since I'm capturing data on the falling edge of 'waitrequest', this really hoses me up, especially since 'readdata' is only valid until the next rising clock edge. Then, 'readdata' clears out its upper 8-bits for some reason. I'm still workin' on it, but any assistance on this would be greatly appreciated. I haven't tried using the flow control signals yet. Thanks, Jon