custom instruction not working in 13.1.3

Moving the xxx_hw.tcl file did require that it was edited by qsys and then hand edited.

# TCL File Generated by Component Editor 13.1
#  Fri Nov 14 15:38:04 GMT 2014
#  DO NOT MODIFY
# 
#  add_imm "add_imm" v1.0
#   2014.11.14.15:38:04
#  add immediate
# 
# 
#  request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1
# 
#  module add_imm
# 
set_module_property DESCRIPTION "add immediate"
set_module_property NAME add_imm
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Custom Instruction Modules"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME add_imm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
# 
#  file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
#  dsl - line below added by hand
set_fileset_property QUARTUS_SYNTH TOP_LEVEL add_imm
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file add_imm.vhd VHDL PATH add_imm.vhd TOP_LEVEL_FILE
# 
#  parameters
# 
# 
#  display items
# 
# 
#  connection point cis0
# 
add_interface cis0 nios_custom_instruction end
set_interface_property cis0 clockCycle 0
set_interface_property cis0 operands 2
set_interface_property cis0 ENABLED true
set_interface_property cis0 EXPORT_OF ""
set_interface_property cis0 PORT_NAME_MAP ""
set_interface_property cis0 CMSIS_SVD_VARIABLES ""
set_interface_property cis0 SVD_ADDRESS_GROUP ""
add_interface_port cis0 ncs_cis0_dataa dataa Input 32
add_interface_port cis0 ncs_cis0_result result Output 32
add_interface_port cis0 ncs_cis0_b b Input 5

-- add_imm.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity add_imm is
        port (
                ncs_cis0_dataa  : in  std_logic_vector(31 downto 0) := (others => '0'); -- cis0.dataa
                ncs_cis0_result : out std_logic_vector(31 downto 0);                    --     .result
                ncs_cis0_b      : in  std_logic_vector(4 downto 0) := (others => '0')  --     .b
        );
end entity add_imm;
architecture rtl of add_imm is
begin
        ncs_cis0_result <= ncs_cis0_dataa + (B"000000000000000000000000000" & ncs_cis0_b);
end architecture rtl; -- of add_imm