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Altera_Forum
Honored Contributor
21 years agoCustom Component
Hi, I created a 2-FIFOs with the following ports clk aclr wr_en data_in rd_en data_out empty(only on the source FIFO) one fifo will be the source and another fifo will be ...
Altera_Forum
Honored Contributor
21 years agooh yeah i almost forgot
i got it working with IRQs, thank you for telling me about it. i'll use your method of using external registers space because you said its more efficient. looking forward for your example program. thanks again! patel