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Altera_Forum
Honored Contributor
Honored ContributorCustom Component
Hi, I created a 2-FIFOs with the following ports clk aclr wr_en data_in rd_en data_out empty(only on the source FIFO) one fifo will be the source and another fifo will be ...
Altera_ForumHonored Contributor
Honored Contributorit is only going to perform one task. at first i thought of using registers but seeing how taking a log of a number takes 300 us at 85MHz, another 2-3 pieces of data could be waiting to be pulled while the log is being done.
yes, i would like to see your little design which will have the processor read/write to the registers when there is something in there. it would help me use it as an example.
