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Altera_Forum
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20 years ago

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Hi, I created a 2-FIFOs with the following ports clk aclr wr_en data_in rd_en data_out empty(only on the source FIFO) one fifo will be the source and another fifo will be ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Actually now that I have seen your code I have a question.

Is the Nios II in this system simply a stage in this FIFO train that does the db calculation? If so I have a simplier idea for you that involves pulling (interrupts are only useful if your system does many things where pulling is wasteful, but if you only perform one task then pulling is actually a better solution).

Long story short in the pulling method I would have the empty/full status of your fifo be a register that you can read from to determine the status of your FIFOs. So for the input fifo if emtpy = 0 you don't read from it, and in your send fifo you wait for full = 0 to put data into it. If you are not sure how to create an external register space let me know and I can send you a dumb little design that I made which has 4 registers sitting in custom logic, and the processor can read/write to them.