Custom Component

Thanks for your reply BadOmen,

I like change my design to handle interrupts, I have a bit of a problem. I am a total noob with dealing with interrupts in C and how the interrupt signal should look like out of the VHDL code.

Here is my VHDL code as of right now

library ieee;
  use ieee.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;
ENTITY top_log IS
    port(
        i_clk               : IN STD_LOGIC;
        i_aclr              : IN STD_LOGIC;
        i_source_data       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        i_source_wrreq      : IN STD_LOGIC;
        i_cpu_rdreq         : IN STD_LOGIC;
        o_cpu_i_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        o_cpu_wait_request  : OUT STD_LOGIC;
        i_cpu_o_data        : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        i_cpu_wrreq         : IN STD_LOGIC;
        i_dest_rdreq        : IN STD_LOGIC;
        o_dest_data         : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
        o_dest_rdy_to_rd_n  : OUT STD_LOGIC
        );
END top_log;
ARCHITECTURE rtl OF top_log IS
COMPONENT log_source_fifo
    PORT
    (
  data  : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
  wrreq  : IN STD_LOGIC;
  rdreq  : IN STD_LOGIC;
  clock  : IN STD_LOGIC;
  q  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
  empty  : OUT STD_LOGIC
    );
END COMPONENT;
COMPONENT log_destination_fifo
    PORT
    (
  data  : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
  wrreq  : IN STD_LOGIC;
  rdreq  : IN STD_LOGIC;
  clock  : IN STD_LOGIC;
  q  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
  empty  : OUT STD_LOGIC
    );
END COMPONENT;
SIGNAL c_dest_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL c_cpu_source_empty : STD_LOGIC;
type sm_wait_request_type is (s_waitrequest_init, s_waitrequest_okay);
signal sm_wait_request: sm_wait_request_type;
BEGIN
o_dest_data <= c_dest_data(13 DOWNTO 0);
LOG_SOURCE : log_source_fifo PORT MAP (
                                       data   => i_source_data,
                                       wrreq  => i_source_wrreq,
                                       rdreq  => i_cpu_rdreq,
                                       clock  => i_clk,
                                       q      => o_cpu_i_data,
                                       empty  => c_cpu_source_empty
                                      );
LOG_DESTINATION : log_destination_fifo PORT MAP (
                                                 data   => i_cpu_o_data,
                                                 wrreq  => i_cpu_wrreq,
                                                 rdreq  => i_dest_rdreq,
                                                 clock  => i_clk,
                                                 q      => c_dest_data,
                                                 empty  => o_dest_rdy_to_rd_n
                                                );
sm_wait_request_machine: process (i_clk, i_aclr)
begin
if i_aclr=&#39;1&#39; then
  sm_wait_request <= s_waitrequest_init;
    o_cpu_wait_request <= &#39;0&#39;;
elsif rising_edge(i_clk) then
  case sm_wait_request is
    when s_waitrequest_init =>
      o_cpu_wait_request <= &#39;0&#39;;
      if c_cpu_source_empty = &#39;0&#39; then
        sm_wait_request <= s_waitrequest_okay;
        o_cpu_wait_request <= &#39;1&#39;;
      end if;
    when s_waitrequest_okay =>
      if i_cpu_wrreq = &#39;1&#39; then
        sm_wait_request <= s_waitrequest_init;
      end if;
  end case;
end if;
end process;
end RTL;

Right now the waitrequest signal goes high once empty signal from the source fifo goes low and the waitrequest signal doesn not go down to 0 until the last piece of data is written into the destination fifo. I can change the code back so it will send a signal to the cpu to tell it data is ready as you suggested in the above post.

here is my c code

#include <stdio.h># include <math.h># include "system.h"# include "altera_avalon_pio_regs.h"
int main (void)
{
 double source_word; 
 double log_word;
 double floor_word;
 double upscaled_word;
while(1)
{
source_word = IORD(TOP_LOG_0_BASE, 0);
log_word = 10*log10(source_word);
upscaled_word = (log_word)*(pow(2,6));
floor_word = floor(upscaled_word);
IOWR(TOP_LOG_0_BASE, 0 , floor_word);
}; 
   return 0;
}

This code is meant to convert MHz into Db(10log10(Mhz)) and upscaled 2^6 so I will get the precision I need. how would i change this code and mapping in the custom component to implement interrupts?

Thanks in advance!