Honored Contributor
Honored ContributorHello,
I seem to have the same problem but I cannot fix it the same way.... I made a driver for the flash memory of my custom board, that seems to be OK since it passes all the tests of the flash_test program (I actually just hardcoded parameters of the CFI-flash driver because my flash is an AMD but non CFI-compliant). The flash programmer did not work at all (unable to synchronise with hardware), so I used a PLL (and a delay reset to allow PLL to stabilize) to increase my design frequency. My oscillator runs at 20Mhz and I tried different multiply factor. I actually don't have a perfect knowledge in PLL so I am not sure that I can multiply my input clock frequency as much as I want, but I tried 40 Mhz (2 x), 50Mhz (5/2 x), and 60Mhz(3 x). With 60 Mhz I dont get anything, I mean I cannot synchronize with hardware. Maybe a 3x factor for the PLL is too much and get unprecise ? With 50 Mhz the flash programmer "randomly" gives different messages, sometimes I get nothing, sometimes I get a message like "wrong start bit", sometimes I have a dump of a JTAG unexpected frame, so there i apparently a problem of communication. With 40 Mhz I always get the same message : unable to open flash device after successfully communicating with device. Does it mean that my flash driver is not as good as I thought (however it passes all tests) ? Does it mean that the JTAG communication works well (I mean has the comunication been tested and the crash happens when the NiosII tries to open the flash device) ? Can someone help me solve this ? Thanks Pod
