Cross clock domain control signal convey

Stratix II EP2S60

one module runs at 400MHz clk.

use a 100MHz clked FSM to control the 400MHz module.

400MHz module stand alone, fmax is around 630MHz, all external control signal left as pins.

Then tried to use a FSM to control the 400MHz module, use FSM registered outputs to drive those pins (wires) of the 400MHz module. Cross clock domain paths failed, clock setup violation due to large clock skew (long path to source register).

Since all the control signals can be asynchronous outputs (leave a value then let 400MHz to read it synchronously), used latches, multiple stages DFF, all not success.

Please help! If I can simply use 100MHz FSM set a value, then let 400MHz fetch this value. (no tight timing concern)

Thanks