Creating ptf file and coe generator

Project is a simple master with and 1 control port.

when i build design i have error:

<div class='quotetop'>QUOTE </div>

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&#39;Master &#39;test_master_0/x_master&#39; has no signal of type &#39;waitrequest&#39; or &#39;waitrequest_n&#39; yet must wait sometimes&#39; OCCURRED on d:/hdk/altera/quartus60/sopc_builder/bin/europa/e_ptf_slave_arbitration_module.pm 11561[/b]

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Codegenerator(simple, black_box now):

use strict;
use europa_all;
use e_avalon_master;
$| = 1;
exit if (0 == @ARGV);
my $project = e_project->new(@ARGV);
my $module = $project->top();
my $Opt = &copy_of_hash($project->WSA());
$Opt->{name} = $module->name();
my $marker = e_default_module_marker->new($module); 
  # GLOBAL PORTS
   e_port->adds({name => "clock", type => "clk",}),
   e_port->adds({name => "reset_n", type => "reset_n",}),
   my @x_ports = (
      ,
      ,
      ,
      ,
      ,
      , << Error, this master exist in generated hdl? but sopc builder don&#39;t see him
   ); 
   my $x_type_map = {
      x_address         => "address",
      x_writedata       => "writedata",
      x_readdata        => "readdata",
      x_read            => "read",
      x_write           => "write",
      x_waitrequest     => "waitrequest",
   };
   $module->add_contents (
      e_avalon_master->adds ({name     => "x_master",type_map => $x_type_map,}),
      e_port->adds(@x_ports)
      );
      $project->output();

I use "copy/paste" metod to write it, but i don&#39;t know where error(in Making arbitration stage).

How can i define master bus(es) in code generator?

(With simple example with comments if possiple)