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Altera_Forum
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13 years ago

Creating Ethernet Frames

I've got an Aria V starter board with Marvell PHY. I'm trying to get some data from the board to the PC over the ethernet. The QSYS system is all wired up and I can do DMAs from an internal memory ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

It is described on page 3-3 of the tse user guide (http://www.altera.com/literature/ug/ug_ethernet.pdf), option "Align packet headers to 32-bit

boundaries (applicable to 32-bit FIFO only)".

This 2-byte padding enabled to align the 14-byte Ethernet packet to 32-bit boundaries so that the rest of the packet is aligned. The Interniche driver uses this to prevent from having to shift every word after the Ethernet header. This option can be turned off it you don't need it (but as said in the documentation in this case it won't work with the Interniche driver any more).