Coverting/Combining SOF and ELF for EPCS

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originally posted by ghavenga@Aug 24 2006, 03:41 PM

a ) control the offset in the epcs (or any flash) where the software is placed. this is different from where it's going to be located once it's loaded into ram - we don't care about that - we need to specify put the software in the epcs at offset blah.

b ) tell the bootloader this offset.

c ) be able to tell where in the epcs the code is loaded from - from the application itself. if this is not possible, we could use the hard coded value from step "a", but it would be really nice to figure that out for step "a" and then have everything else just configure automagically.

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Greg, not sure why you want to do this - it would be easier to reserve space for whatever you want to do inside your firmware image or at the very end of everything. I&#39;m assuming that you want to keep the FPGA config and some other data together in the EPCS and change the firmware image independently of those other two items.

Keep in mind that the EPCS is two things:

1) a magic device to load FPGA configuration. If I&#39;m not mistaken the FPGA automatically loads from EPCS starting at offset 0 so you can regard that as a given

2) a general purpose serial flash device where you can write and read (using the HAL flash API) whatever you want following the FPGA config.

To address your questions:

a) I haven&#39;t tried this but you should be able to use the flash programmer to write any location in the EPCS, given the right command line options.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif The bootloader in question is part of your NIOS design. I think it&#39;s inside the EPCS component so you&#39;d have to dig up the sources of the bootloader (e.g. components/altera_nios2/sdk/src/boot_loader_sources/boot_loader_epcs_bits.S) and modify it to boot from a specific address instead of directly after the FPGA config file. I could envision different ways of configuring that address but the simplest approach would be to write some additional bytes directly following the FPGA config bytes that say "skip n bytes to get to the beginning of the image."

If you haven&#39;t done so already, take a look at boot_loader_epcs_bits.S. I think this is the code that ends up in the EPCS component itself and is compiled into the FPGA configuration so that&#39;s where you&#39;d have to add code to support the reserved gap you&#39;re after. I haven&#39;t looked at how the bootloader ends up inside the FPGA configuration image but it must be part of the SOPC compile process.

c) Once you&#39;ve modified boot_loader_epcs_bits.S you should have some fixed location inside the EPCS component itself that you can read with normal I/O operations. Again, I haven&#39;t done this but I can&#39;t see why it shouldn&#39;t work.

Good luck and keep us posted,

Andrew