Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCounting Watchdog Resets
Hello I have a NIOS 2 application that has an Interval timer configured as a Watchdog timer. This works as expected in my code, causing a CPU reset as appropriate for the circumstances. Howeve...
Altera_ForumHonored Contributor
Honored Contributorsomething like:::
entity ent is
port(
clk : in std_logic;
timeout_pulse : in std_logic;
reset_request : out std_logic;
avs_read : in std_logic;
avs_read_data : out std_logic_vector(31 downto 0)
);
end ent;
architecture stl of ent is
signal cnt : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(timeout_pulse = '1') then
cnt <= cnt + 1;
end if;
end if;
end process;
reset_request <= timeout_pulse;
avs_read_data <= cnt;
end stl;
