Counting Watchdog Resets

You could route the reset pulse to outside the sopc system. Then, create a custom component with a counter that increments the count every time the wd count is input, as well as trigger the system reset. Just have to catch the edge of the wd input signal, make sure you don't count too many, and make sure the count doesn't get reset based on the reset signal.

something like:::

entity ent is
port(
clk : in std_logic;
timeout_pulse : in std_logic;
reset_request : out std_logic;
avs_read : in std_logic;
avs_read_data : out std_logic_vector(31 downto 0)
);
end ent;
architecture stl of ent is
  signal cnt : std_logic_vector(31 downto 0);
begin
process(clk)
begin
  if(rising_edge(clk)) then
    if(timeout_pulse = '1') then
      cnt <= cnt + 1;
    end if;
  end if;
end process;
reset_request <= timeout_pulse;
avs_read_data <= cnt;
end stl;

Thank you very much kbs972 for your response.

I have a similar approach. I do not need to count the watchdog resets, but want to distinguish between a watchdog and a normal external reset for built-in test.

Thanks for your reply. I have been working on this and have found a solution, for my purposes anyway. I decided that since I could not identify a Watchdog reset, I would identify the normal POR instead. I created a VHDL latch and placed it outside the NIOS. The latch would be set by the reset signal from outside the FPGA, generated from a seperate reset chip. I added a single output port to my NIOS and connected it to the latch reset. I also added a single input port to check the latch output state. In software my program would check the status of the latch first and if it was not set (reset), then the reset did not happen due to a POR so it must be a Watchdog reset. I could then count the resets when the latch was reset, but not if it was set. This seems to work okay in my application. I hope my explaination is clear and you find the idea useable.

Thanks for your quick reply. I think I understand the spirit of your solution and will implement it this way.