Counting Watchdog Resets

Thanks for your reply. I have been working on this and have found a solution, for my purposes anyway. I decided that since I could not identify a Watchdog reset, I would identify the normal POR instead. I created a VHDL latch and placed it outside the NIOS. The latch would be set by the reset signal from outside the FPGA, generated from a seperate reset chip. I added a single output port to my NIOS and connected it to the latch reset. I also added a single input port to check the latch output state. In software my program would check the status of the latch first and if it was not set (reset), then the reset did not happen due to a POR so it must be a Watchdog reset. I could then count the resets when the latch was reset, but not if it was set. This seems to work okay in my application. I hope my explaination is clear and you find the idea useable.