Honored Contributor
Honored Contributorwhen I suggested testing the tx/rx chain with the feedback loop deactivated I wanted a sanity check of your chain. Ideally you should have testbench for every module by reading reference outputs from matlab into testbench and check for bit true comparison. That is what we do in the industry. Moreover you need to scale the outputs of each module to some practical resolution e.g 16 bits signed yet I see your dynamic range too high.
Repeat the chain sanity test by checking that what you send from Tx as random symbols is recovered by Rx and check that at symbol rate. I mean your overall rx chain should decimate until reaching symbol rate then pass it through a simple slicer and check pattern. I did some experiments on this design in matlab running 1 Msamples and it locks for all cases nicely (symbols at +1 all = single tone, symbols at +1/-1 = single tone with jitter and random data. Though I used complex I/Q RF to avoid extra filter (for speed). So I am convinced it should lock eventually). It does not lock if I changed input to QPSK or 16QAM. The main point I noticed was that I have to update the NCO word once only every say 10 error updates (ignore 9) and revert back to initial nco word. The scaling is essential to match your phase resolution word of nco. You will get a nice oscillation that converges to perfect result or so (I got zero jitter at .01Fs). I did not use proportional term. Remember what aplies to software dsp does not apply to FPGA nco. DSP engineers do not know about fpga and are only orientated to their platform. Our nco has one control over phase and frequency (nco increment value).
