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The above code should prove the concept.
The feedback point is at this equation below
bb(i) = rf_signal(i).*exp(j*2*pi*fc*i+j*phase_offset).*exp(-j*PhErr(i-1));
The expression exp(-j*err) means rotate phase 90 degrees *err clockwise while frequency is unchanged.
This may suit software based dsp but in rtl the nco is controlled via inc value which controls both phase and frequency.
So keep on modelsim
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Wonderful! This qualifies my previous analysis.
Here is the result of a test with the loop activated and a small phase offset.
Output from loop filter is shifted right by 7 and fed to NCO word.
https://www.alteraforum.com/forum/attachment.php?attachmentid=10467 https://www.alteraforum.com/forum/attachment.php?attachmentid=10468 As I shift the output with a smaller number i.e. as I divide by a smaller number, meanders increase in the specified period of time (400 microseconds),
but it keeps rising.
I don't know if this will lock and settle.
What do you think? I am thinking of programming the FPGA with this design and capture signals using SignalTap, if it locks eventually, I should see the same
input pattern... do you recommend doing that?
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