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originally posted by doofus64@Feb 8 2006, 01:31 PM
when i try to add a simple file like the below in component editor it fails.
????????????? it happens for all file, more comleks than this eksample to.
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error: command "quartus_map --generate_hdl_interface=e:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd ce_temp_directory/ce_temp_quartus_project" returned 3
error: quartus ii analysis & synthesis was unsuccessful. 1 error, 0 warnings
error: processing ended: wed feb 08 21:25:04 2006
error: elapsed time: 00:00:03
error: e:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd.xml does not exist --- Quote End ---
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doofus64,
Did you try to compile the VHDL file first in Quartus II to see if it will pass compilation before importing the VHDL file into the Component Editor?
Your VHDL or Verilog design must pass Quartus compilation first before you start to import the HDL file as a component into SOPC builder. If you noticed from the log output "quartus_map.exe" is the start of analysis and mapping of Quartus II Synthsis (if you use Quartus II scripting) and you have no logic in your design to map. I would expect the importing of incomplete HDL code in component editor to error out very early in the process.
Regards,
-ATJ