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Altera_Forum
Honored Contributor
Honored ContributorComponent editor advice
I have an avalon memory slave with this simple interface (export side is not listed) -- inputs from avalon:
signal address : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
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Altera_ForumHonored Contributor
Honored ContributorHello Mir
I also needed a read hold time to interface an isdn chip, the only solution was to add an extra delay by extra flipflops in the top bdf on the address lines. Also we had an extra address bus for this chip. Altera should think about this.
