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Altera_Forum's avatar
Altera_Forum
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21 years ago

Component editor advice

I have an avalon memory slave with this simple interface (export side is not listed) -- inputs from avalon: signal address : IN STD_LOGIC_VECTOR (18 DOWNTO 1); ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Hello Mir

I also needed a read hold time to interface an isdn chip, the only solution was to add

an extra delay by extra flipflops in the top bdf on the address lines. Also we had

an extra address bus for this chip.

Altera should think about this.