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Altera_Forum's avatar
Altera_Forum
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21 years ago

Component editor advice

I have an avalon memory slave with this simple interface (export side is not listed) -- inputs from avalon: signal address : IN STD_LOGIC_VECTOR (18 DOWNTO 1); ...
Altera_Forum's avatar
Altera_Forum
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21 years ago

Hi all,

I also have problems when designing user components. What I have figured out is:

- if a waitrequest-signal is added, you cannot enter setup (and hold) times

- there are some differences between 'Interface to User Logic' and 'Create New Component'

- in 'Create New Component' setup times are not possible when units 'cycles' is selected (even if you add a clk signal as the dialog suggests)

- in 'Interface to User Logic' you can enter setup and hold-times in 'cycles' but they are displayed in fractions of cycles

This concerns Quartus / NIOS II Version 5.0.

I also would like to have a hold time for read access to get a behaviour similar to Motorola Timing and other asynchronous MCUs. A problem is, that at the end of a read-cycle all signals leave their active state simultaneously and produce spikes in sub decoders (In my design NIOS replaces a 68k MCU). Are there any undocumented features?

Mike