Comments on Embedded Operating Systems for the Cyclone V

Hi Joe,

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The processor would run in a loop that executes every 300usec. During that time it would receive data from the FPGA side, process the data and then DMA the data to a PCIe channel. The DMA should occur at or very near the same time for every 300usec loop, such as at 150usec within the 300usec loop. Can any RTOS run with this types of constraints?

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Sure, an RTOS can run with that constraint. However, have you determined that the required processing can be completed in the time required? It does not matter if your RTOS can schedule tasks in real-time, if your processor cannot perform the processing.

It would be easier to recommend a solution if you could provide information on what the processing is. If that processing can be implemented in an FPGA, or can be accelerated by an FPGA, then your software would not need to be real-time.

Cheers,

Dave