Code in tightly coupled memory

Ok, now I know how to address tc_data, thanks.

But I intend to use TCM for ISRs (Interrupt Service Routine). I need to know, how to define an "Separate Hardware Interrupt Stack". I haven't found any examples.

Better I explain my intentions in more detail.

My ISR looks like this:

static void handle_CPU2_interrupts(void* context, alt_u32 id) __attribute__ ((section (".exceptions")));

static void handle_CPU2_interrupts(void* context, alt_u32 id)

{

OSSemPost(IRQSem); // <-- benefit from a seperated exception stack ?

IOWR_ALTERA_AVALON_PIO_EDGE_CAP(CPU1_INTHAND_BASE, 0x1);

}

void task(void* pdata)

{

[... init ...]

while (1) {

OSSemPend(IRQSem, 0, &err); <-- event waiting

[ ... do something ... ]

}

}

SoPC:

I set the exception address, on the Core Nios II tab, in the

Exception Vector: Memory: list, to tightly_coupled_instruction_memory_s1.

RTOS:

I use µC/OS-II.

Problems:

1. ISR response takes ~16 µs.

2. From OSSemPost, in the ISR, to OSSemPend, in task, it takes ~34 µs.

Any chances to reduce these times ?

My possible solutions:

-> Try TCM

-> Try VIC -> will reduce ISR response certainly (<<16µs)

If I had examples I wouldn't struggle with TCM and I can test possible performance improvements. I would appreciate any comments / suggestions. I need this for my bachelor thesis.

Thanks any help very much.

Regards,

R2-D2

@chris72

your thread "timer interrupt with rtos-ii"

similar to my project.