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- tightly coupled code memory MUST have both a access connection to Nios TC instr. port and a connection to Nios data master, with same addresses
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Not strictly true. If you put the .rodata elsewhere, and load the code from another Avalon master (or from within the fgpa image itself), then the nios cpu doesn't need data access to its own code.
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- tightly coupled code memory need only the connection to Nios TC data port.
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I presume you meant 'data'. True - provided nother external nees to initialise it.
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- ALT_LOAD_SECTION_BY_NAME() *MUST* be called for all section not explicitly mentioned in system library properties (namely if you map something into them with the attribute directive); infact loader (jtag too) places these objects at paddr addresses, while the application must take care to copy it to correct vaddr.
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This is because your linker script is wrong.
You should be able to get the linker to put the data items such that both paddr and vaddr are correct (the current vaddr value).
For instance, if you want to initialize a large block of M9K memory, and your main code is in TC memory. then you don't want the initialisation data appended to your code - there just isn't space there.
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