Code in tightly coupled memory

The linker output:

    LOAD off    0x0001a968 vaddr 0x03008000 paddr 0x02024d68 align 2**0
         filesz 0x00000160 memsz 0x00000160 flags r-x
    LOAD off    0x0001aac8 vaddr 0x0300a000 paddr 0x02024ec8 align 2**0
         filesz 0x00000020 memsz 0x00000020 flags rw-

probably isn't what you want.

The 'vaddr' (virtual address) value is the address that the code is linked for. This is the address that other parts of the nios code will use in order to reference this area.

The 'paddr' (physical address) is the address where the loader will write the data.

Note that the 'paddr' follow on from the previous segment - rather than matching the 'vaddr'.

This might be what you want if you are trying to get the program loaded into a single memory block (ie a ROM image) - but something at run time has to copy the data from whatever virtual address the 'paddr' gets mapped to onto the correct virtual address.

If you are loading directly from the elf file - as the JTAG loader does - you probably want the 'paddr' and 'vaddr' values to match.

If you can't read/write the tc_code area it may be that you don't have the correct access setup in the sopc builder.

You need to give the nios cpu data port access to the tightly coupled instruction memory (at the same address) to allow the code to be written to it (you mustn't do this for the tightly coupled data areas, since that makes two slaves try to respond to the same address).

If you are loading code by some external means (ie not by running code in the nios cpu), and move all the .rodata (etc) sections from instruction memory to data memory then you don't need data access to the code area.

If fact, any build that uses tightly coupled instruction and data memory (so probably doesn't contain a data cache, and may have a minimal instruction cache to allow jtag (etc) bootstrap) really needs the readonly data linked with the initailised read/write data and placed in the tightly coupled data memory, not the tightly coupled instruction memory. This removes the Avalon MM transfers used when accessing the rodata.