Code for FFT using SGDMA

If the CPU is configured to have a data cache then I would expect intermittent cache coherency issues with that code. Since you are using malloc to allocate the memory I would replace those calls to the uncacheable malloc instead which will make sure that the pointer returned will perform cache bypassing automatically as well as flush the cache before returning the pointer.

Using IOWR based on the pointer returned from malloc is not enough to ensure no cache coherency issues. If the memory that was allocated by malloc happened to be cached before hand and you attempt to use IOWR to write to those memory locations the data in the cache will get written out instead of what you pass into IOWR. This is not a bug because you are essentially treating the memory range as cacheable and non-cacheable at the same time. That is why I recommend using the uncache malloc calls instead which will avoid this automatically (see Nios II software developers handbook for more details.)