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AKhed's avatar
AKhed
Icon for New Contributor rankNew Contributor
7 years ago

Clock signal jumper connection

Hello, I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from e...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Basically, we will try to keep the clock path clean.

Jumpers may not add noise. But there will be a small stub created while routing, which will effect the signal to small extend, also which will act as antenna and add noise.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)