Honored ContributorI am debugging a custom board with 16MB sdram ( 32bit-data-width, share avlon bus). Please help me to state some guideline of caculating the PLL clock shift degree of sdram. Thank you.
Honored ContributorDepending on how fast you run the SDRAM it should work on a -3.5ns shift wrt the Avalon Clock in most cases. This value was picked since it works over a large range of frequencies. If you want to calculate this value and fine tune it I recommend opening the SSRAM component in SOPC Builder and reading the documentation that comes with it. Also it discusses the phase shift for SSRAM but the concept applies to SDRAM as well (make sure you have the SDRAM datasheet in front of you so you know what its tco is for example).
