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Altera_Forum's avatar
Altera_Forum
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16 years ago

clock edge help!

hi everybody! I'm working in modelsim verilog for 2weeks now, and i need some help. i used before to work on vhdl which functions as verilog. what i want to do is an adder (x+y=z ) with a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Please check your module Add_Hard . Inside it you are declared clock as input but you assign a value

initial clock=1;

please remove this statement & try again