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The IDE tends to link the initialisation data for 'other' memory sections to immediately follow the .code - then add instructions to copy it into the relevant memory area. This might be what you want if your code is in SDRAM, but doesn't work in many other cases [1].
In your case you'll need to rebuild the fpga image in order to change the actual memory contents of the memory cells.
I've not tried to use the EPCS loader (we load through the PCIe slave) but I suspect Altera try to make it appear as something other than a small memory block! (Much like the way they hid the code/data areas inside the JTAG unit)
[1] I had problems using the JTAG loader for a system with 8k of tightly coupled instruction memory and a 12k data area containing lookup tables. The linker/loader were trying to load it all to the code space the copy the data area. I had to use a custom linker script (that generated multiple program segments) in order to get the JTAG loader to load the image.
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There are not multiple data records in the boot EPCS image - it's one big block of data. What then copies the various initialized code and data to onchip memory? I have 10k of onchip memory code and initialized variables. If I break in crt0.s, they are already initialized. Maybe the jtag loads them, but when running from EPCS, how do they get initialized? Did they become part of the hardware configuration?
If I read you right, you're saying the EPCS 512 bytes is not memory per se, but logic that is initialized by SOPC builder and just looks like memory to the Cyclone?
Thank you,
Bill
Honored Contributor
