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Altera_Forum
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16 years ago

CFI Flash doesn't read correcty after reset

I have a Stratix II GX with 2MBytes Flash in 8 bit mode and 512kBytes SRAM in 8 bit mode. The Flash memory is hooked up properly, in that most of my applications run just fine, but I'm having t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Jake,

Many thanks. I have implemented two things which seems to have cured this - at least in part. 1) as per your suggestion, the FPGA reset pin which also drives the CPU reset pin now drives the Flash reset pin as well and 2) after the FPGA comes out of reset it waits 2 seconds before releasing the CPU reset.

This works now for power-on-reset and for pressing the reset button, but if the CPU issues its own reset it still needs to reset the Flash manually. Exactly why the Flash would not be in read mode after boot up is still a puzzle to me, but maybe it is to do with the latest 9.1 CFI driver?

Anyway, all working well enough now!

Cheers,

Simon