--- Quote Start ---
originally posted by jesse@Feb 16 2005, 12:03 PM
i have not performed any speed tests but have looked at the verilog & sopc builder timing used to implement that component. it is a very simple interface, with setup/hold/wait-state delays in accordance with the cf specification, using true ide mode (http://www.sandisk.com/pdf/oem/cf-manual-10.7.pdf). thus i would not expect the interface to go much slower than cf would natively allow. --- Quote End ---
Thanks, Jesse. I was involved in doing some evaluation on the CF component and the read data transfer rate was in the neighbourhood of 100k/second, very low. Now, this was a very simple test and may not have been done under optimal circumstances, so I just wanted to know if it's worth putting more effort into getting the test right to try to crank up the speed. I had a look at the verilog code for the CF but I'm a "VHDL man" so all I could see was that it does true IDE mode. You just confirmed my suspicion that it should be able to run much faster.
--- Quote Start ---
originally posted by jesse@Feb 16 2005, 12:03 PM
if i get to doing any throughput tests (i'm actively working with cf a bit this week) i'll try to post something further. --- Quote End ---
If it's not too much trouble, that would be greatly appreciated.
Thanks again.
Sandor
Honored Contributor
