Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

cat /proc/meminfo

I have a 2.6.16 uClinux kernel running on an Altera Cyclone II DSP Dev Board (finally!) but now I am confused about the information I get back from cat /proc/meminfo. The kernel is located on th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

I'm working with the standard 256Mb DDR2 SDRAM that came packaged with the Altera Cyclone II board. In SOPC Builder, with the Target Board specified to the Cyclone II DSP Board (EP2C35), the DDR2 SDRAM Controller Megacore Function defaults to 256Mb properly.

The SDRAM component is connected to the CPU instruction master and data master.