cat /proc/meminfo

The Nios II instruction master won't support more than 256 MB of contiguous address space. SOPC Builder shouldn't even allow you to connect a 256 MB memory to a Nios II instruction master.

The CPU's data master does not have this limitation. Are you only connecting to the processor's data master, then? If so, then I'm not sure how Linux/uCLinux would handle this sort of situation.

Cheers,

- slacker

I'm working with the standard 256Mb DDR2 SDRAM that came packaged with the Altera Cyclone II board. In SOPC Builder, with the Target Board specified to the Cyclone II DSP Board (EP2C35), the DDR2 SDRAM Controller Megacore Function defaults to 256Mb properly.

The SDRAM component is connected to the CPU instruction master and data master.

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originally posted by daniellew@Aug 25 2006, 10:08 AM

i'm working with the standard 256mb ddr2 sdram that came packaged with the altera cyclone ii board. in sopc builder, with the target board specified to the cyclone ii dsp board (ep2c35), the ddr2 sdram controller megacore function defaults to 256mb properly.

the sdram component is connected to the cpu instruction master and data master.

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To the best of my knowledge, the standard designs (shipped with the kit) only allow you to access 64MB of the 256MB DIMM. (what does SOPC Builder tell you, not the DDR Megawizard??) Did you modify the design and, if so, how did you get it to work? The last time I tried (circa Nios II 5.0/Quartus II 5.0), SOPC Builder (appropriately, as the processor and toolchain don&#39;t support it) would not allow me to increase the address span, that the instruction master sees, beyond the 256MB limit.

I&#39;m not saying I don&#39;t believe you, I&#39;m just stating that, in my experience, the state you&#39;re in is not possible to reach when using the tools correctly.

Cheers,

- slacker

I am still using Nios II 5.0 and Quartus 5.0. And indeed you are correct. Although the MegaWizard shows it as 256 MB, the base and end addresses in SOPC add up to 64MB (0x4000000 to 0x7FFFFFF)...

So this leads me to the next question...

I can successfully load my kernel to the sdram. Now I just want to save ~200MB of data on the rest of the sdram using a C++ application I will develop in the Nios II IDE. Will the C++ app. be able to access the addresses outside of those 64MB it thinks are available? (And if not, why in the world would Altera put a 256MB SDRAM on a board if you can&#39;t even use it??)

Thanks for your help.

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originally posted by daniellew@Aug 25 2006, 11:16 AM

now i just want to save ~200mb of data on the rest of the sdram using a c++ application i will develop in the nios ii ide. will the c++ app. be able to access the addresses outside of those 64mb it thinks are available? (and if not, why in the world would altera put a 256mb sdram on a board if you can&#39;t even use it??)

thanks for your help.

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The C/C++ application won&#39;t be able to see anything beyond what&#39;s hooked up in your current SOPC Builder system.... (64MB).

As to why things were done this way, I think it&#39;s because it&#39;s only the processor&#39;s instruction master that has this limitation. Any of the other IP (Avalon or otherwise) can handle address spans greater than 256MB, including the data master and the DMA. As to why this was the example design shipped with the kit..... probably historical, though you could request an update.

My advice would be to change your SOPC Builder design and squeeze the kernel into the SRAM (if possible), and only connect the processor&#39;s data master to the 256MB DIMM. You could use a DMA to transfer data in/out of the DDR DIMM, as well.

Beware that you&#39;re likely to hit timing issues.... You may have to use the clock-crossing FIFOed bridge, that is located in the "projects" section of this Forum website.

In other words, you have a lot of options, but none of them are trivial.

Good luck :-)

Cheers,

- slacker